5 research outputs found
Sphinx: A Secure Architecture Based on Binary Code Diversification and Execution Obfuscation
Sphinx, a hardware-software co-design architecture for binary code and
runtime obfuscation. The Sphinx architecture uses binary code diversification
and self-reconfigurable processing elements to maintain application
functionality while obfuscating the binary code and architecture states to
attackers. This approach dramatically reduces an attacker's ability to exploit
information gained from one deployment to attack another deployment. Our
results show that the Sphinx is able to decouple the program's execution time,
power and memory and I/O activities from its functionality. It is also
practical in the sense that the system (both software and hardware) overheads
are minimal.Comment: Boston Area Architecture 2018 Workshop (BARC18
Sphinx: a secure architecture based on binary code diversification and execution obfuscation
Sphinx, a hardware-software co-design architecture for binary code and runtime obfuscation. The Sphinx architecture uses binary code diversification and self-reconfigurable processing elements to maintain application functionality while obfuscating the binary code and architecture states to attackers. This approach dramatically reduces an attacker’s ability to exploit information gained from one deployment to attack another deployment. Our results show that the Sphinx is able to decouple the program’s execution time, power and memory and I/O activities from its functionality. It is also practical in the sense that the system (both software and hardware) overheads are minimal.Published versio
BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox
In this work, we introduce a platform for register-transfer level (RTL)
architecture design space exploration. The platform is an open-source,
parameterized, synthesizable set of RTL modules for designing RISC-V based
single and multi-core architecture systems. The platform is designed with a
high degree of modularity. It provides highly-parameterized, composable RTL
modules for fast and accurate exploration of different RISC-V based core
complexities, multi-level caching and memory organizations, system topologies,
router architectures, and routing schemes. The platform can be used for both
RTL simulation and FPGA based emulation. The hardware modules are implemented
in synthesizable Verilog using no vendor-specific blocks. The platform includes
a RISC-V compiler toolchain to assist in developing software for the cores, a
web-based system configuration graphical user interface (GUI) and a web-based
RISC-V assembly simulator. The platform supports a myriad of RISC-V
architectures, ranging from a simple single cycle processor to a multi-core SoC
with a complex memory hierarchy and a network-on-chip. The modules are designed
to support incremental additions and modifications. The interfaces between
components are particularly designed to allow parts of the processor such as
whole cache modules, cores or individual pipeline stages, to be modified or
replaced without impacting the rest of the system. The platform allows
researchers to quickly instantiate complete working RISC-V multi-core systems
with synthesizable RTL and make targeted modifications to fit their needs. The
complete platform (including Verilog source code) can be downloaded at
https://ascslab.org/research/briscv/explorer/explorer.html.Comment: In Proceedings of the 2019 ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays (FPGA '19
Ultra-thin dielectric insertions for contact resistivity lowering in advanced CMOS: Promises and challenges
International audienceIn this paper, in order to provide a comprehensive overview of the opportunities and limitations of the metal/insulator/semiconductor contacts approach, expected performance based on ideal contact simulations as well as key practical aspects are presented. While the former give us a glimpse of the theoretical potential of this paradigm, mainly to contact nFETs, the latter highlights concerns about the electrical characterization of such contacts along with issues occurring during their physical implementation. (c) 2017 The Japan Society of Applied Physic